1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device used in a mobile device.
2. Discussion of Related Art
Due to increases in the demand for mobile devices, such as cellular phones, efforts have been made to develop mobile products with a variety of functions. Mobile devices having larger data storage capacities and higher operating speeds are needed to support these functions. For example, a cellular phone that supports moving images and photographing functions may need a memory with a large storage capacity, such as a dynamic random access memory (DRAM), to store large amounts of data.
A cellular phone may include a memory with a small storage capacity, such as a flash memory, to store operating system (OS) programs and application programs, which support the functions. There are different types of flash memories, e.g., a NOR-type flash memory, an AND-type flash memory, and a NAND-type flash memory. The NOR-type flash memory, the AND-type flash memory, and the NAND-type flash memory may be differentiated from one another according to respective memory cell array structures. The NOR-type flash memory includes a NOR-type memory cell array that has reduced parasitic resistance, compared to the AND-type and NAND-type flash memories. Thus, the NOR-type flash memory can operate faster than the AND-type and NAND-type flash memories. However, the NOR-type flash memory occupies a larger area and is more expensive than the AND-type and NAND-type flash memories. The AND-type flash memory includes an AND-type memory cell array, and the NAND-type flash memory includes a NAND-type memory cell array. The AND-type and NAND-type memory cell arrays occupy less area per memory cell compared to the NOR-type flash memory. Thus, the AND-type and NAND-type memory cell arrays may be produced having a higher density than the NOR-type memory cell array. Therefore, the AND-type and NAND-type flash memories may occupy a smaller area and are cheaper than the NOR-type flash memory. However, the AND-type and NAND-type flash memories operate slower than the NOR-type flash memory.
The NOR-type flash memory was widely adopted in a cellular phone for high-speed operations of the cellular phone. However, the NAND-type flash memory has been more widely adopted in a cellular phone than the NOR-type flash memory because the NAND-type flash memory is cheaper than the NOR-type flash memory. To overcome the limitations of the NAND-type flash memory, e.g., slower operation, a predetermined program stored in the NAND-type flash memory may be copied into a memory with a large storage capacity, such as a DRAM, which can operate at a higher speed than the NAND-type flash memory, and a processor may be enabled to access the DRAM to execute the predetermined program. This technique is disclosed in U.S. Pat. No. 6,587,393 entitled “Semiconductor Device Including Multi-chip”.
FIG. 1 is a block diagram of a system having a DRAM 20. Referring to FIG. 1, a central processing unit (CPU) 12, the DRAM 20, a direct memory access (DMA) 13, and a flash memory 14 are connected to one another via a memory bus 11. The DMA 13 is connected between the conventional DRAM 20 and the flash memory 14. To execute a predetermined program, an operating system (OS) program and application programs stored in the flash memory 14 are transferred to the DRAM 20 via the DMA 13 and stored in a predetermined area of the DRAM 20. The OS program and application programs stored in the flash memory 14 are copied into the DRAM 20. Thereafter, the CPU 12 accesses the DRAM 20, which operates at high speed, to execute the predetermined program.
FIG. 2 is a block diagram of the DRAM 20 of FIG. 1. Referring to FIG. 2, the DRAM 20 includes a row address buffer 21, a column address buffer 22, a row decoder 23, a column decoder 24, and a memory cell array 27. The memory cell array 27 has a predetermined area 28 for storing the OS program and application programs received from the flash memory 14. However, if a wrong address signal is input to the DRAM 20 due to, for example, program errors or a malfunction of a chipset during a write operation, wrong data may be written on the predetermined area 28. As a result, a system including the DRAM 20 may malfunction. In addition, it may be difficult to detect such wrong data written on the predetermined area 28.